Apparatus and method for responding to data retention loss in a non-volatile memory unit using error checking and correction techniques

ABSTRACT

In a non-volatile memory unit such as a flash memory unit, the degradation of charge can result in an error during a read operation. By using the error checking and correction techniques, a determination can be made whether a detected error can be corrected and, if correctable, is the consistent with charge degradation at that bit position displaying the error. When a correctable error is detected, the signal group address and the correction pattern are stored and an interrupt request flag applied to the central processing unit. When the interrupt flag is processed, the central processing unit, using the signal group address and the correction pattern, restores the charge of the bit position in the memory unit. In this manner, further read operations involving the restored bit position will not repeat the corrected error.

FIELD OF THE INVENTION

[0001] This invention relates generally to the data processing systemsand, more particularly, to error checking and correction techniques usedin connection with a non-volatile memory unit such as a flash memoryunit.

BACKGROUND OF THE INVENTION

[0002] Referring to FIG. 1, a block diagram of a data processing system10 that includes error checking and correction capability according tothe prior art is shown. The data processing system 10 includes a centralprocessing unit 11 and a memory unit 12. The central processing unit 11exchanges signals with apparatus not shown, but which, for example, caninclude peripheral devices, keyboard signals, etc. The centralprocessing unit 11 applies address signals to the main memory 121 and tothe error checking and correction memory 122. The central processingunit 11 also applies data signals to the main memory 121 and the errorchecking and correction memory 122. The main memory 121, during a readoperation, applies signals to a check bit calculation unit 123. Thecheck bit calculation unit 123 and the error checking and correctionmemory 122 apply signals to the syndrome calculation unit 124. Thesyndrome calculation unit 124 applies data signals and the syndrome unit124 applies syndrome signals to the bit correction unit 125.

[0003] The operation of the data processing system 10 can be understoodas follows. The central processing unit 11, in a write operation of asignal group, generates the error checking and correction signalsassociated with the signal group to be stored in the main memory 121.The signal group is then stored in the main memory 121 and the errorchecking and correction signals are stored in the error checking andcorrection memory 122 at the same address. In a read operation, theaddressed signal group in the main memory 121 is applied to the checkbit calculator 123 while the associated (i.e., at the same address)error checking and correction signals in the error checking andcorrection memory 122 are transferred to the syndrome calculation unit124. The check bit calculation unit 123 provides error checking andcorrection signals to the syndrome calculation unit 124. Based on acomparison of the signals from the check bit calculation unit 123 andthe error checking and correction signals from the error correction codememory, the syndrome calculation unit 124 provides a group of syndromesignals that identifies the correctable bit position in the data signalgroup. The group of syndrome signals is applied to the bit correctionunit 125. In the bit correction unit, the data signal group from themain memory 121 is corrected and transferred to the central processingunit 11.

[0004] While the foregoing operation has proven successful forcorrecting data signal groups stored in a non-volatile memory, oneproblem is that this error will need to be corrected for every readoperation. However, when an error in a different position in the datasignal group is identified, the single bit error correcting procedureswill not be adequate and the data processing unit forced to respond toan uncorrectable error.

[0005] A need has therefore been felt for apparatus and associatedmethod for using an error checking and correction algorithm forcorrecting a bit in a data signal group. It would be another feature ofthe apparatus and associated method to identify a failing bit as a causeof an error in the data signal group. It would be yet another feature ofthe apparatus and associated method to restore the charge on the failingbit in the main memory or error checking and correction memory.

SUMMARY OF THE INVENTION

[0006] The aforementioned and other features are accomplished, accordingto the present invention, by providing the main memory with errorchecking and correction apparatus and with apparatus identifying asignal group error, detected by the error checking and correctionapparatus, as a the result of a failing bit position in the main memoryor the error checking and correction memory. A failing bit positionoccurs in a non-volatile main memory implemented, for example, in flashtechnology when charge leakage changes the state of original or defaultstate of the bit location. When a correctable data signal group error isidentified in a read operation, the error is corrected and the datasignal group is forwarded to the central processing unit. In addition,the address and the location of the location of the error are stored. Aninterrupt flag is available to the central processing unit. When thecentral processing unit can be interrupted, the central processing unitrestores the location in the main memory where the error originatedbased on the stored address and location. The error correcting apparatuswill thereafter not be burdened with correcting errors in the same bitlocation. Additionally, it is sometimes desirable to leave unprogrammedlocations in the memory where tables can be updated without erasing thelocation contents. When the existing table is to e updated, the oldinformation is programmed to be all logic “0”s. The correspondingcorrection bits are programmed to be all logic “0”s. The new table withits new correction bits is then programmed into new, usually successivelocations that were previously all logic “1”s (all erased bits). Tofacilitate this requirement, additional circuitry is added to suppressoptionally error corrections when the data and the correction bits areall in the logic “1”s or logic “0”s state.

[0007] Other features and advantages of the present invention will bemore clearly understood upon reading of the following description andthe accompanying drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a block of a central processing unit and a main memoryunit having error checking and correction capability according to theprior art.

[0009]FIG. 2 is a block diagram of a central processing unit havingerror checking and correction capability as well as failing bitidentification and restoration apparatus according to the presentinvention.

[0010]FIG. 3 is flow chart illustrating the response to an errordetected during a read operation according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0011] 1. Detailed Description of the Drawings

[0012]FIG. 1 has been described with respect to the related art.

[0013] Referring next to FIG. 2, a block diagram of data processingsystem 20 according to the present invention is illustrated. The centralprocessing unit 11, the main memory unit 121, the error checking andcorrection memory 122, and the syndrome calculation unit 124 performessentially the same functions as described in FIG. 1. The bitcorrection unit 225 has an additional function as compared to the bitcorrection unit 125 of FIG. 1. In particular, when the bit location thatis failing displays a logic “1” as compared to a correct logic “0”, aninterrupt request flag indicative of a failing zero bit position isgenerated. The present invention has three control signals that areillustrated by the erase condition valid 221, the correctable errorinterrupt enable 223, and the interrupt on zero fail only. These controlsignals are applied to the interrupt flag request unit 226. Based onthese signals, the correction pattern latch unit 227 and the addresslatch 228 will store appropriate signal groups until the centralprocessing unit 11 responds to a signal from the interrupt request flagunit 226. When the signal from the interrupt request unit 226 isserviced, the contents of the correction pattern latch 227 and theaddress latch 228 are forwarded to the central processing unit 11.

[0014] The erase condition valid signal 221 provides that when a groupmemory of locations have had no data stored therein, the storagelocations are in the erase condition and are indicative of logic “1”s,then no correction is done. Normally, the erased condition wouldgenerate a non-correctable error. Setting the erase condition valid flagallows this error to be ignored.

[0015] The interrupt on zero fail only signal provides that an interruptrequest flag will be set when, in the normal correction of signalgroups, the correction is to change a logic “1” to a logic “0”. Thecorrection is consistent with a charge loss in a bit location. Thecorrection of a logic “0” to a logic “1” is not consistent with a chargeloss in a bit location in the present example. When a correctable errormeeting the foregoing requirements is identified, then a signal from thebit correction unit 225 is applied to the interrupt request flag unit.The results of the syndrome calculation unit 124 are latched in thecorrection pattern latch unit 227 until the central processing unit canservice the interrupt.

[0016] The correctable error interrupt enable signal allows correctableerrors optionally to generate an interrupt request. When the error isnot correctable, then the central processing unit 11 is notified of anon-correctable error and the currently executing process is aborted.

[0017] Referring to FIG. 3, a process for responding to a detected erroraccording to the present invention is shown. In step 31, the centralprocessing unit is executing instructions of a program. In step 32, aread operation for retrieval of signal groups from the memory unit isinstituted. A determination is made by the error checking and correctionapparatus whether the retrieved signal group has an error. in step 33.When no error is detected in step 34, the procedure returns to step 31.When an error is detected I step 33, then a determination is madewhether the detected error (or errors) is correctable. When the detectederror is not correctable in step 34, then the operation of theprocessing unit or at least that program is aborted. When in step 34 thedetected error is correctable, then the syndrome bits are calculated instep 35. In step 36, a determination is made whether the error isconsistent with a failing bit in the main memory. When the detectedfailing bit is not consistent with a failing bit location in the mainmemory, then the erroneous bit is corrected in step 37 and the processreturned to step 31 for execution of the program. When, in step 36, thedetected error is consistent with a failing bit location, then theaddress of the signal group in which the error was detected and thecorrection pattern are stored in step 38. In step 39, an interrupt flagis set. The procedure then corrects the error and returns to step 31. Instep 40, the interrupt flag is serviced by the central processing unit.The charge on the failing bit location is restored and the processreturns to step 31.

[0018] 2. Operation of the Preferred Embodiment

[0019] The operation of the present invention can be understood asfollows. The invention relies on the fact that certain non-volatilememories, such as flash memory units or EEPROM (electrically erasableprogrammable read only memory) units, have a first state, i.e., a logic“0” state determined by a stored charge. When the stored charge decays asufficient amount, then the bit location will be read as logic “1”. Theerror checking and correction apparatus will determine the presence ofan error state. In the example given above, the data signal groupsstored in main memory is 64 bits. The check bit signal groups stored inthe error checking and correction memory unit are 8 bits in lengths. Thesyndrome bits would therefore be 72 bits in length. Such an errorchecking and correction technique can identify a single correctableerror or can identify two errors that cannot be corrected. As will beclear to those skilled in the art, more elaborate error checking andcorrection schemes are available and can be used advantageously with thepresent invention. When the error checking and correction unitdetermines that a bit signal that should be a logic “0” is a logic “1”,this error can be caused by a decay of the charge at the memorylocation. The response of the present invention, upon detection of anerror that could be the result of decay of charge from a bit location,is to restore the charge at the bit location. The restoration of chargeis the result of setting an interrupt flag. In addition, the address andthe correction pattern are stored of the signal group having the errorare stored. When the central processing unit responds to the interruptflag, the address and correction pattern are transferred to the centralprocessing unit. The central processing unit can restore the charge ofthe failing bit location or can restore either the signal grouplocations in the main memory or in the error checking and correctingmemory unit depending on the position of the correctable error.

[0020] While the invention has been described with respect to theembodiments set forth above, the invention is not necessarily limited tothese embodiments. Accordingly, other embodiment variations, andimprovements not described herein, are not necessarily excluded from thescope of the invention, the scope of the invention being defined by thefollowing claims.

What is claimed is:
 1. A memory unit comprising: a memory portion havingstorage units storing data bits; a memory portion storing errorcorrection bits; an error checking and correction unit; and registers tohold the location of one or more corrected bits.
 2. The memory unit asrecited in claim 1 wherein the error checking and correction unitincludes circuitry for requesting an interrupt and/or for setting a flagwhich can be polled, when a failing bit can be corrected.
 3. The memoryunit as recited in claim 1 wherein the error detection and correctionunit includes circuitry for requesting an abort condition when a failingbit is detected which can not be corrected.
 4. The memory unit asrecited in claim 2 wherein the memory is composed of storage unitsstoring data bits that can be set to one of two states, wherein any ofthe data bits may be changed to a first state independently of the otherbits, the resulting state being a programmed state, wherein all of thedata bits of a plurality of data bits must be set to the second statesimultaneously, the second state being an erased state, the memory unitfurther comprising: circuitry to store the location of a correctableerror; and circuitry to generate an interrupt request; circuitry to seta flag bit only when the correctable error is a bit that has beenchanged from the programmed state to the erased state.
 5. A memory unitcomprising: storage units storing data bits; storage units storing errorchecking and correction bits; and an error detection and correction unitwherein the memory unit contains circuitry to optionally exclude thecondition where all of the data bits and error detection and correctionbits are in the erased state from generating bit correction.
 6. A memoryunit comprising: storage units for storing data bits; storage units forstoring error correction bits; an error detection and correction unit;circuitry to optionally exclude the condition where all of the data bitsand error detection and correction bits are in the programmed state fromgenerating bit correction.
 7. A data processing system, the dataprocessing system comprising: a central processing unit; and a memoryunit, the memory unit including: a main memory, the main memory storingdata signal groups in a plurality of addresses; an error checking andcorrection memory, the error checking and correction memory storingerror correcting signals for each data signal group in the main memoryat the same address in the error checking and correction code memory;error checking and correction apparatus for identifying and correctingat least one error in a data group accessed by a read operation; andfailing bit apparatus, the failing bit apparatus identifying when acorrectable error is the result of a failing location.
 8. The dataprocessing system as recited in claim 7 wherein the failing bitapparatus includes: an address storage unit; a correction patternstorage unit; and an interrupt flag unit, the interrupt flag unitissuing an interrupt flag when an error is detected that can be theresult of failing bit memory location.
 9. The data processing system asrecited in claim 8 further comprising an all logic “1”s detection unitfor determining whether all of the signals from a main memory and errorchecking and correction memory are all logic “1”.
 10. The dataprocessing system as recited in claim 7 wherein the main memory and theerror checking and correction memory are implemented in a technologyselected from the group consisting of flash technology and EEPROMtechnology.
 11. A method of responding to an error in a signal groupretrieved from a non-volatile memory unit, the method comprising: whenthe error is correctable, correcting the error in the signal group usingerror checking and correction techniques; and when the error isconsistent with a failing bit position, restoring the charge associatedwith the bit position.
 12. The method as recited in claim 11 wherein therestoring step includes the steps of: storing the address of the signalgroup having the error; storing the correction pattern identifyinglocation of the error in the signal group; and providing an interruptflag to the central processing unit indicating the need to restore a bitlocation in the memory unit.
 13. The method as recited in claim 11further comprising implementing the main memory and the error checkingand correction memory in a technology selected from the group consistingof flash technology and EEPROM technology.
 14. A memory unit comprising:a non-volatile main memory unit; a non-volatile error memory for storingerror checking and correction signals for a signal group in the mainmemory having the same address; error checking and correction apparatus,the error apparatus generating a correction pattern identifying thelocation of an error in an addressed signal group and the associatederror signals, the error apparatus generating a restore signal when theerror is consistent with a failing bit location; flag apparatus storingthe associated correction pattern and the associated address in responseto the restore signal, the flag apparatus generating an interrupt flagin response to the restore signal.
 15. The memory unit as recited inclaim 14 wherein the stored correction pattern and the stored addressare transferred to the central processor for restoration of the failingbit location when the central processing unit services the interrupt.16. The memory unit as recited in claim 14 wherein the error checkingand correction apparatus includes an all logic “1”s detection unit, theall logic “1”s detection unit determining when the signals stored in themain memory and in the error signal memory are all logic “1”s.
 17. Thememory unit as recited in claim 14 wherein the main memory and the errorchecking and correction memory are implemented in a technology selectedfrom the group consisting of flash technology and EEPROM technology.